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| AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Introduction The AGR09180EF is a high-voltage, gold-metalized, laterally diffused metal oxide semiconductor (LDMOS) RF power transistor suitable for cellular band, code-division multiple access (CDMA), global system for mobile communication (GSM), enhanced data for global evolution (EDGE), and time-division multiple access (TDMA) single and multicarrier class AB wireless base station amplifier applications. This device is manufactured on an advanced LDMOS technology, offering state-of-the-art performance, reliability, and thermal resistance. Packaged in an industry-standard CuW package capable of delivering a minimum output power of 180 W, it is ideally suited for today's RF power amplifier applications. Table 1. Thermal Characteristics Parameter Thermal Resistance, Junction to Case Sym R JC Value 0.35 Unit C/W Table 2. Absolute Maximum Ratings* Parameter Sym Value Unit Drain-source Voltage VDSS 65 Vdc Gate-source Voltage VGS -0.5, +15 Vdc Total Dissipation at TC = 25 C PD 500 W Derate Above 25 C -- 2.86 W/C Operating Junction TemperaTJ 200 C ture Storage Temperature Range TSTG -65, +150 C * Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 3. ESD Rating* AGR09180EF HBM MM CDM Minimum (V) 500 50 1000 Class 1B A 4 Figure 1. AGR09180EF (flanged) Package Features Typical performance ratings are for IS-95 CDMA, pilot, sync, paging, traffic codes 8--13: -- Output power (POUT): 38 W. -- Power gain: 18.25 dB. -- Efficiency: 27%. -- Adjacent channel power ratio (ACPR) for 30 kHz bandwidth (BW): (750 kHz offset: -45 dBc) (1.98 MHz offset: -60 dBc). -- Input return loss: 10 dB. High-reliability, gold-metalization process. High gain, efficiency, and linearity. Integrated ESD protection. Si LDMOS. Industry-standard packages. 180 W minimum output power. * Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. PEAK Devices Agere employs a human-body model (HBM), a machine model (MM), and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and JESD22-C101A (CDM) standards. Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed. AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Electrical Characteristics Recommended operating conditions apply unless otherwise specified: TC = 30 C. Table 4. dc Characteristics (Measurements made on 1/2 of device) Parameter Off Characteristics 300 Drain-source Breakdown Voltage (VGS = 0, ID = 400 A) Zero Gate Voltage Drain Leakage Current (VDS = 28 V, VGS = 0 V) On Characteristics Forward Transconductance (VDS = 10 V, ID = 1.0 A) Gate Threshold Voltage (VDS = 10 V, ID = 600 A) Drain-source On-voltage (VGS = 10 V, ID = 1.0 A) Table 5. RF Characteristics Parameter Output Capacitance (VDS = 28 Vdc, VGS = 0, f = 1 MHz) Reverse Transfer Capacitance (VDS = 28 Vdc, VGS = 0, f = 1 MHz) Symbol COSS Min -- -- Typ 46 2.4 Max -- -- Unit pF pF Gate Quiescent Voltage (VDS = 28 V, IDQ = 2 x 850 mA) VGS(TH) VDS(ON) VGS(Q) GFS -- -- -- -- 12 3.8 -- 4.8 -- -- -- Vdc Vdc Vdc S Gate-source Leakage Current (VGS = 5 V, VDS = 0 V) Symbol V(BR)DSS IGSS IDSS Min 65 -- -- Typ -- Max -- Unit Vdc -- -- 6 200 16 Adc Adc 0.06 Dynamic Characteristics (Measurements made on 1/2 of device) CRSS Linear Power Gain (VDS = 28 V, POUT = 38 W, IDQ = 2 x 850 mA) Functional Tests (in Supplied Test Fixture) Agere Systems Supplied Test Fixture) (Test frequencies (f) = 865 MHz, 880 MHz, 895 MHz) GL 17.5 180 -- IMD VSWRI -- -- -- 18.25 210 58 -30 2:1 -- -- -- -- -- dB W % dBc -- Drain Efficiency (VDS = 28 V, POUT = P1dB, IDQ = 2 x 850 mA) Output Power (VDS = 28 V, 1 dB compression, IDQ = 2 x 850 mA) P1dB Ruggedness (VDS = 28 V, POUT = 180 W, IDQ = 2 x 850 mA, f = 880 MHz, VSWR = 10:1, all angles) Input VSWR Third-order Intermodulation Distortion (100 kHz spacing, VDS = 28 V, POUT = 180 WPEP, IDQ = 2 x 850 mA) No degradation in output power. AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Test Circuit Illustrations R5 VGG R7 FB1 R3 Z11 R1 Z4 Z5 C18 Z7 Z9 C28 Z29 C24 C23 C22 Z17 Z19 C20 Z21 2A C45 1A Z23 3 DUT 1B Z22 C51 Z28 C29 C30 C31 C32 C49 C44 Z33 Z35 Z38 RF OUTPUT C33 C34 COAX2 C35 VDD C1 C2 C3 RF INPUT Z1 C4 C5 C6 C7 C8 Z13 Z15 Z27 Z25 C46 Z24 Z26 Z31 C19 COAX1 Z2 Z3 Z6 C17 Z8 R2 C21 Z37 C47 C48 2B Z20 Z12 Z14 Z16 Z18 C26 Z30 R6 VGG R8 FB2 R4 Z32 C50 Z34 Z36 VDD C27 C25 PINS: 1A. DRAIN 1B. DRAIN 2A. GATE 2B. GATE 3. SOURCE C52 Z10 C14 C15 C16 C9 C10 C11 C12 C13 C36 C37 C38 C39 C40 C41 C42 C43 A. Schematic Parts List: Kemet(R) 1206 size chip capacitor: C3, C4, C11, C12, C32, C40: 0.1 F, C1206C104KRAC7800. Murata (R) 0805: C5, C13, C31, C39: 0.01 F, GRM40X7R103K100AL. Sprague (R) tantalum chip capacitor, 35 V: C1, C2, C9, C10, C33, C34, C41, C42: 10 F; C35, C43: 22 F. Johanson Giga-Trim(R) variable capacitors, 27291SL: C19, C48:0.8 pF--8.0 pF. ATC(R) chip capacitor: C7, C15, C20, C22, C25, C29, C37, C47: 10 pF, 100B100JW; C8, C16, C17, C18, C28, C36, C49, C50: 47 pF, 100B470JW; C21: 3.9 pF, 100B3R9BW; C23, C26: 6.8 pF, 100B6R8BW; C24, C27: 4.7 pF, 100B4R7BW; C44, C51: 12 pF 100B120JW; C45, C52: 2.0 pF, 100B2R0BW; C46: 5.6 pF 100B5R6BW. 0603 size chip capacitors: C6, C14, C30, C38: 220 pF. UT-141A: Coax1, Coax2: 50 , semi-rigid coaxial cable. Kreger(R) ferrite bead: FB1, FB2: 2743D19447. Taconic (R) ORCER RF-35: board material, 1 oz. copper, 30 mil thickness, r = 2.55. Microstrip line: Z1, Z38 0.572 in. x 0.084 in.; Z2, Z4, Z36, Z37 1.834 in. x 0.084 in.; Z3, Z5, Z34, Z35 0.106 in. x 0.110 in.; Z6, Z7 0.0785 in. x 0.110 in.; Z8, Z9 0.782 in. x 0.110 in.; Z10, Z11 1.182 in. x 0.060 in.; Z12, Z13 0.128 in. x 0.700 in.; Z14, Z15 0.209 in. x 0.700 in.; Z16, Z17, Z18, Z19, Z24, Z25 0.100 in. x 0.700 in.; Z20, Z21, Z26, Z27 0.050 in. x 0.700 in.; Z22, Z23 0.498 in. x 0.700 in.; Z28, Z29 1.715 in. x 0.065 in.; Z30, Z31 0.651 in. x 0.110 in.; Z32, Z33 0.100 in. x 0.110 in. 1206 size chip resistor, 0.25 W: R1, R2: 51 , RM73B2B510J; R3, R4: 56 k , RM73B2B563J; R5, R6: 12 , RM73B2B120J; R7, R8: 1.2 k , RM73B2B122J. B. Component Layout Figure 2. Test Circuit AGR 09180 EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Typical Performance Characteristics 0.11 0.12 0.38 0.13 0.37 0.14 0.36 0.1 50 45 0 .09 0.4 1 0.4 110 0.39 100 0.9 90 1.0 0.15 0.35 80 0.6 60 0.4 12 0 0. 07 5 65 0. 0. 0. 06 0. 44 43 0 13 T CI PA CA IV AN PT CE US ES CE ) / Yo (+jB 0.7 2 0.2 70 0.0 0.4 75 EN T (+ j X/ Z ,O o) R 14 5 0.4 0 5 0.0 6 15 0 CE CO M 0.4 PO N 0.6 4 GEN ERA TO R 0.4 > 7 160 80 0.8 RE AC TA N 1. 0 A RD S TOW 0.48 90 IN D 0.0 > WA VELE N GTH 170 0.49 0.6 0.2 0.3 0.4 0.5 0.7 0.8 1.2 1.4 1.8 0.1 0.9 1.0 0.0 D LOA D < OW A R 7 180 HST N GT -170 EL E V WA -90 -160 RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo) 0.2 0.49 0.1 0.4 o) jB/ Y E (NC MHz (f) (f1) (f2) (f3) ZL ZS (Complex Source Impedance) (Complex Optimum Load Impedance) 0.7 - j1.46 3.32 + j2.44 0.7 - j1.54 3.34 + j2.36 0.7 - j1.64 3.38 + j2.28 Note: Measured drain to drain and gate to gate, respectively. DRAIN (1) GATE (2) ZS ZL SOURCE (3) INPUT MATCH DUT OUTPUT MATCH Figure 3. Series Equivalent Input and Output Impedances TA 1. 0.2 ZS f3 f1 0.48 0.6 0. 8 0 -85 1.6 2.0 0. 8 Z0 = 7 0.6 f1 ZL f3 0.4 85 U CT IVE 1. 0 1.4 0.2 0 0.8 .08 1.2 40 70 55 35 0. 4 0.3 0.2 0.1 AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Typical Performance Characteristics (continued) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 ACPR (dBc)Z ACP+ ACPACP1+ ACP1- 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 78 83 POUT (W)ZZ Test Conditions: VDD = 28 Vdc, IDQ = 1700 mA, TC = 30 C, IS-95 CDMA PILOT, PAGING, SYNC, TRAFFIC CODES 8--13, FREQUENCY = 880 MHz, OFFSET 1 = 750 kHz, 30 kHz BW, OFFSET 2 = 1.98 MHz, 30 kHz BW. Figure 4. ACPR vs. POUT 20 19 18 POWER GAIN (dB)Z 17 16 15 14 13 12 11 10 860 RETURN LOSS POWER GAIN POUT = 38 W 0.0 -2.0 -6.0 -8.0 -10.0 -12.0 -14.0 -16.0 -18.0 -20.0 900 INPUT RETURN LOSS (dB)Z -4.0 POUT = 220 W 865 870 875 880 885 890 895 FREQUENCY (MHz)Z Test Conditions: VDD = 28 Vdc, IDQ = 1700 mA, TC = 30 C, WAVEFORM = CW. Figure 5. Power Gain and Return Loss vs. Frequency AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Typical Performance Characteristics (continued) 22 20 POWER GAIN (Pg) (dB)Z 18 16 14 12 10 8 6 4 2 0 0 20 40 60 80 100 120 140 160 180 200 220 240 865 MHz 880 MHz 895 MHz POUT (W) Test Conditions: VDD = 28 Vdc, IDQ = 1700 mA, TC = 30 C, WAVEFORM = CW. Figure 6. Power Gain vs. Power Out 240 220 200 180 160 140 120 100 80 60 40 20 0 POUT (W)Z 865 MHz 880 MHz 895 MHz POUT EFFICIENCY 0.0 0.4 0.8 1.2 1.6 2.0 PIN (W)Z 2.4 2.8 3.2 865 MHz 880 MHz 895 MHz 3.6 4.0 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 Test Conditions: VDD = 28 Vdc, IDQ = 1700 mA, TC = 30 C, WAVEFORM = CW. Figure 7. Power Out and Drain Efficiency vs. Input Power DRAIN EFFICIENCY (Eff.) (%)Z AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Typical Performance Characteristics (continued) 20.5 20.0 POWER GAIN (Pg) (dB)Z IDQ = 2300 mA IDQ = 2000 mA 19.5 19.0 18.5 18.0 17.5 17.0 16.5 IDQ = 1400 mA IDQ = 1700 mA IDQ = 1100 mA 0 20 40 60 80 100 120 140 160 180 200 220 240 OUTPUT POWER (POUT) (W)Z Test Conditions: VDD = 28 V, FREQUENCY = 880 MHz. Figure 8. Power Gain vs. Power Out 330 310 290 270 250 230 210 190 170 150 130 110 90 70 865 MHz 880 MHz 895 MHz POUT (W)Z 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN (W)Z Test Conditions: VDD = 28 V, IDQ = 1700 mA, TC = 30 C. PULSE WIDTH = 8 s, DUTY FACTOR = 10%. Figure 9. Power Out vs. Input Power AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Typical Performance Characteristics (continued) 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 IM3IM3+ IM5IM5+ IMD dBcZ IM7IM7+ 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 OUTPUT POWER (POUT) WPEPZ Test Conditions: VDD = 28 V, IDQ = 1700 mA, TC = 30 C. F1 = 880 MHz and F2 = 880.1 MHz. Figure 10. Third-order Intermodulation Distortion vs. Power Out AGR09180EF 180 W, 865 MHz--895 MHz, N-Channel E-Mode, Lateral MOSFET Package Dimensions All dimensions are in inches. Tolerances are 0.005 in. unless specified. PINS: 1A. DRAIN 1B. DRAIN 2A. GATE 2B. GATE 3. SOURCE 1A 1B 3 AGERE PEAK DEVICES AGR19K180U AGR09180EF YYWWLL XXXXX XXXX ZZZZZZZ 2A 2B XXXX - 4 Digit Trace Code Agere Systems Inc. |
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